A data processing apparatus includes a buffer storage having high speed and small capacity memory elements used in a central processing unit (CPU). On the other hand, a main storage includes low speed and large capacity memory elements. Data blocks, which are separated in the main storage, are copied and stored in the buffer storage so that it is possible to achieve high speed access from the central processing unit to the main storage by accessing the data blocks copied into the buffer storage.
In general, a set associative method is utilized for a mapping operation from the main storage to the buffer storage. In this method, a plurality of WAYs are provided on a line which is accessed by a part of an address of the data block. The data and the block address except for bits used in the line address, are registered on the WAY. In the buffer storage, a space which stores the data is called a data portion (DATA), and a space which stores the block address is called a tag portion (TAG).
Further, there is a store-in method as a control method of the buffer storage. In this method, when there is no object data for a fetch access and store access to the buffer storage, the data block including the object data is moved from the main storage to the buffer storage (i.e., move-in operation MI). When performing the fetch access, the object data in the buffer storage is transferred from the data block in the main storage to an access source. When performing the store access, the object data is stored in the buffer storage. When the object block for the move-in operation is a data block which was stored in the past, or when another calculation device sharing the main storage requires use of the data block which was stored in the past, the object block is moved from the buffer storage to the main memory (i.e. move-out operation MO).
On the other hand, there are two kinds of addresses for accessing the buffer storage, i.e., one is a method of using only a part of a byte index of a logical address, and the other is a method of using both a part of a page address of the logical address and a part of the byte index of the logical address. The present invention relates to a buffer control storage system using the latter.
In this case, the logical address is used as an address for accessing from a calculation control unit to a main storage unit, and there are two types of addresses in accordance with a state of the calculation control unit. One is a real address, and this address is converted to an absolute address to access the main memory by means of a prefix conversion means using a prefix-register. The other is a virtual address, and this address is converted to the absolute address by means of an address conversion means using an address conversion table.
In both address types, the address is divided into the page address for an upper portion of the address and the byte index for a lower portion of the address. Further, before and after the prefix conversion or address conversion, values in the byte index are not changed, and values in the page address are changed. For example, when address bits are given by 01 to 31 and a page size is given by 4 Kbytes, 19 bits (01 to 19) denote the page address portion, and 12 bits (20 to 31) denote the byte index portion.
Further, the central processing unit simultaneously accesses the address conversion buffer and the TAG portion of the buffer storage to achieve high speed pipe-line processing. In this case, the TAG portion cannot be accessed by using the absolute address which is obtained as a result of the retrieval for the address conversion buffer. Accordingly, in general, a part of the byte address of the logical address is used as the line address for the buffer storage.
When the page size is given by 4 Kbytes and the block size is given by 64 bytes, the logical address which can be used as the line address for the buffer storage is given by bits 20 to 25 so that it becomes 64 bytes.times.64 bytes=4 Kbytes per one way (WAY). In this method, the number of the WAY is increased to increase capacity of the buffer storage. However, when increasing the number of the WAY, it is necessary to increase the number of the comparison circuits for comparing the absolute address obtained by the address conversion buffer with the absolute address obtained by the TAG portion, or to increase the number of the selection circuits for selecting data of each WAY read from the DATA portion.
As another method of increasing the number of lines without increasing of the number of the WAY, both a part of the byte address of the logical address and a part of the page address are used as the line address for the buffer storage. In this case, depending on values of the prefix-register or the address conversion table, the block having the same absolute address may be registered on different lines of the buffer storage. For example, when the page size is given by 4 Kbytes and the block size is given by 64 bytes, and when bits 18 to 25 of the logical address are used as the line address of the buffer storage, the block having the same absolute address may be registered on four lines since bits 18 and 19 are variable for the logical address and the absolute address. This is well-known as a problem of a synonymity to persons skilled in the art.
In the present invention, a line address, which is shown by the logical address bit and applied as an address requested, is called a basic line address. Further, a line address, which is obtained by change of bits of the page address, is called a synonymic line address. In the central processing unit having the buffer storage and using the store-in method, a part of the page address and a part of the byte index are given as the line address so that the present invention can effectively control the buffer storage.